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User's Guide
GDM12864A LCM
TM
(Liquid Crystal Display Module)
XIAMEN OCULAR LCD DEVICES CO., LTD. ??????????????
South 5F., Guang Xia Bldg. Torch Hi-tech Develop. Area, Xiamen, China 361006 Tel: (0592)6026045 Fax: (0592)6026021
GDM12864A LCM
Use's Guide
Contents
Chapter 1. Introduction to ITM-12864A LCM 1
Features Mechanical Specifications Temperature Characteristics External Dimensions Application Diagram Electro- Optical characteristics Interface Pin Connections Electrical Absolute Maximum Rating (KS0107B) DC Electrical Characteristics (KS0107B) Electrical Absolute Maximum Rating (KS0108B) DC Electrical Characteristics (KS0108B) 1 1 1 2 3 4 5 6 6 7 7
Chapter 2. Driver IC (KS0107B) Function Description
Introduction AC Characteristics Master Mode Slave Mode Functional Description RC Oscillator Timing Generation Circuit Data Shift & Phase Select Control 8 9 9 10 11 11 11 12
8
Chapter 3. Driver IC (KS0108B) Function Description
Introduction AC Characteristics Operating Principles & Methods Display Control Instruction 13 13 16 19
13
Chapter 1 Introduction to GDM12864A LCM
1
CHAPTER 1
Introduction to ITM-12864A LCM
ITM-12864A is a dot matrix graphic LCD module which is fabricated by low power COMS technology. It can display 128*64 dots size LCD panel using a 128*64 bit-mapped Display Data RAM (DDRAM). It interfaces with an 8-bit microprocessor.
Features
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Display format: 128*64 dots matrix graphic STN yellow-green mode Easy interface with 8-bit MPU Low power consumption LED back-light Viewing angle: 6 O'clock Driving method : 1/64 duty , 1/6.7 bias LCD driver IC: KS0108B(2 ? )? KS0107B Connector: Zebra
Mechanical Specifications
Item Module Size(W*H*T) Viewing Area(W*H) Number of Dots Dot Size(W*H) Dot Pitch(W*H) Module Size With B/L Dimension 93.0*70.0*10.0 72.0*40.0 128.0*64.0 0.48*0.48 0.52*0.52 93.0*70.0*15.0 Unit mm mm PCS mm mm mm
Temperature Characteristics
Parameter Operating temperature Storage temperature Symbol Topr Tstg Rating 0 ~ +50 -20 ~ +70 Unit ? ?
Chapter 1 Introduction to GDM12864A LCM
2
Figure 1. External Dimensions
PIN SIGNAL PIN SIGNAL
1 Vss 11 DB4
2 VDD 12 DB5
3 V0 13 DB6
4 D/I 14 DB7
5 R/W 15 CS1
6 E 16 CS2
7 DB0 17 RES
8 DB1 18 VEE
9
10
DB2 DB3 19 A 20 K
*NOTE: 1.All units are mm. 2.Tolerances unless otherwise specified ? 0.2.
INTECH
LCD
MODULE
ITM-12864A
Chapter 1 Introduction to GDM12864A LCM
3
Figure 2. Application Diagram
SEG1
.... SEG64
COM64 SEG65
.... SEG128
..
LCD panel (128X64)
COM1
C64 C1 R M FRM CLK1 CLK2 CL2 VDD SHL FS MS PCLK2 DS2 DS1 VSS
CR
C
KS0107B
S1
S64 M FRM CLK1 CLK2 CL2
KS0108B
(Bottom view)
E RW RS DB[0:7] RESETB CS3 CS1B CS2B VSS VEE
VEE V5 V4 V3 V2 V1 V0
ADC VDD V0 V1 V2 V3 V4 V5
VSS VDD
12
V0 V1
MPU
E RW RS DB[0:7] RESETB CS2 CS1
VSS
V2 V3 V4 V5
VSS 12
VEE
CS2B VSS VEE ADC VDD V0 V1 V2 V3 V4 V5
CS1B E RW RS DB[0:7] RESETB
CS3
S1 S64
KS0108B
(Bottom view)
M FRM CLK1 CLK2 CL2
*Note 1/64 duty, 1/6.7 bias VDD>V1>V2>V3>V4>V5>VEE
Chapter 1 Introduction to GDM12864A LCM
4
Electro-Optical characteristics
TN Type (Twisted Nematic ) Item Symbol ?2 -?1 Viewing Angle f Contrast Ratio Response Time (rise) Response Time (fall) Cr tR tF Min. 40 Typ. 4 110 110 Max. Unit deg. ms ms Condition Cr = 2.0 ?=20? f = 0? ?=20? f = 0? ?=20? f = 0? Condition Cr = 2.0 ?=20? f = 0? ?=20? f = 0? ?=20? f = 0? Note 1,2 3 4 4
STN Type (Super Twisted Nematic ) Item Symbol Min. 70 ?2 -?1 Viewing Angle -90 f Contrast Ratio Response Time (rise) Response Time (fall) Cr tR tF -
Typ. 4 110 110
Max. +90 -
Unit deg. ms ms
Note 1,2 3 4 4
1. Definition of angle |E & |O
2. Definition of viewing angle |E 1 & |O 2
Cr Y(|O=180 |I ) |E 1 2.0 |E 1 20 |I |E 2 |E 2
|I |E 1<20 <|E 2
Y'(|O=0 )
|I
3. Definition of contrast Cr
4. Definition of optical response
100% Intensity Selected Dots
B Off Nonselected Dots Intensity 100% 10% 100% Driving Voltage tR Time tF On 90% Off
0%
A Set Point Cr = ( A / B ) p
Negative : P = -1 Positive : P = +1
Chapter 1 Introduction to GDM12864A LCM
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Interface Pin Connections
Pin No. 1 2 3 4 Symbol VSS VDD V0 D/I I/O Type Description Supply Supply Supply Ground Power supply
LCD driver supply voltage
Data input/output pin of internal shift register MS SHL DIO1 Output Output Input Output DIO2 Output Output Output Input
5
R/W
H H H L L H L L Read or Write
RW Description H Data appears at DB[7:0] and can be read by the CPU while E= H CS1B=L,CS2B=L and CS3=H. L Display data DB[7:0] can be written at falling edge of E when CS1B=L, CS2B=L and CS3=H.
6
E
Enable signal
E H L Description Read data in DB[7:0] appears while E= "High". Display data DB[7:0] is latched at falling edge of E.
7 8 9 10 11 12 13 14 15 16
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CS1 CS2
I/O
Data bus [0~7]
Bi-directional data bus
I
Chip selection When CS1=H,CS2=L, select IC1
17
RESETB
I
When CS1=L,CS2=H, select IC2 Reset signal. When RSTB=L
? 1? ON/OFF
register becomes set by 0.(display off)
? 2? display start line register becomes set by 0 (Z-address 0 set, display from line 0) ? 3? After releasing reset , this condition can be changed only by instruction.
18 19 20
VEE A K
Power
VEE is connected by the same voltage. Back-light anode Back-light cathode
Chapter 1 Introduction to GDM12864A LCM
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Electrical Absolute Maximum Ratings (KS0107B)
Parameter Operating voltage Supply voltage Driver supply voltage Symbol VDD VEE VB VLCD Rating -0.3 ~ +7.0 VDD-19.0 ~ VDD+0.3 -0.3 ~ VDD+0.3 VEE-0.3 ~ VDD+0.3 Unit V V V V Note *1 *4 *1,2 *3,4
*Notes: *1. Based on VSS = 0V *2. Applies to input terminals and I/O terminals at high impedance. (Except V0L, V1L, V4L, and V5L) *3. Applies to V0L, V1L, V4L, and V5L. *4. Voltage level: VDD=V0=V1=V2=V3=V4=V5=VEE
DC Electrical Characteristics(KS0107B)
(VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85? ) Item Symbo Condition Min. l Operating voltage VDD 4.5 Input voltage VIH 0.7VDD VIL VSS VOH VOL Input leakage current ILKG OSC Frequency fosc On Resistance (Vdiv-Ci) Operating current RONS IDD1 IDD2 Supply Current Operating Frequency IEE fop1 fop2 output voltage IOH= -0.4mA IOL= 0.4mA VIN= VDD ~ VSS Rf=47kO2% Cf=20pF5% VDD-VEE=17V Load current150?A Master mode 1/128 Duty Master mode 1/128 Duty Master mode 1/128 Duty Master mode External Duty Slave mode VDD-0.4 -1.0 315 50 0.5 Typ. 450 Max. 5.5 VDD 0.3VD
D
Unit V
Note
*1
0.4 +1.0 585 1.5 1.0 0.2 0.1 600 1500
*2 ?A kHz kO mA *3 *4 *5 kHz *1
Notes *1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2, M , and CL2 in the input state. *2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M , and CL2 in the output state. *3. This value is specified about current flowing through VSS. Internal oscillation circuit: Rf=47kO, cf=20pF Each terminals of DS1, DS2, FS, SHL, and MS is connected to VDD and out is no load. *4. This value is specified about current flowing through VSS. Each terminals is DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD,MS is connected to VSS and CL2, M, DIO1 is external clock. *5. This value is specified about current flowing through VEE, Don't connect to VLCD (V1~V5).
Chapter 1 Introduction to GDM12864A LCM
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Electrical Absolute Maximum Ratings(KS0108B)
Parameter Operating voltage Supply voltage Driver supply voltage Symbol VDD VEE VB VLCD Rating -0.3 ~ +7.0 VDD-19.0 ~ VDD+0.3 -0.3 ~ VDD+0.3 VEE-0.3 ~ VDD+0.3 Unit V V V V Note *1 *4 *1,3 *2
*Notes: *1. Based on VSS = 0V *2. Applies the same supply voltage to VEE. VLCD=VDD-VEE. *3. Applies to M, FRM, CLK1,CLK2, CL, RESETB, ADC, CS1B, CS2B,CS3, E, R/W, RS and DB0~DB7. *4. Applies V0L,V2L,V3L and V5L. Voltage level: VDD=V0=V1=V2=V3=V4=V5=VEE
DC Electrical Characteristics(KS0108B)
(VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85? ) Item Symbol Condition Min. Operating voltage VDD 4.5 Input High voltage VIH1 0.7VDD VIH2 2.0 Input Low voltage VIL1 0 VIL2 VOH VOL ILKG ITSL IDIL RONS IDD1 IDD2 IOH= -0.2mA IOL= 1.6mA VIN= VSS ~ VDD VIN= VSS ~ VDD VIN= VEE ~ VDD VDD-VEE=15V Load current100?A During Display During Access Access Cycle=1MHz 0 2.4 -1.0 -5.0 -2.0 Typ. Max. 5.5 VDD VDD 0.3VD
D
Unit V
Note *1 *2 *1 *2 *3 *3 *4 *5 *6
Output High Voltage Output Low Voltage Input leakage current Three-state (OFF) Input Current Driver Input leakage current On Resistance (Vdiv-Ci) Operating current
0.8 0.4 +1.0 5.0 2.0 7.5 0.1 0.5
?A
kO mA
*8 *7 *7
Notes *1. CL, FRM, M, RSTB, CLK1, CLK2 *2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7 *3. DB0~DB7 *4. Except DB0~DB7 *5. DB0~DB7 at high impedance *6. V0, V1, V3, V3, V4, V5 *7. 1/64 duty , FCLK=250KHZ, Frame Frequency=70HKZ, Output: No Load *8. VDD-VEE=15.5V V0L>V2L>= VDD-2/7(VDD-VEE)>V3L= VEE+2/7(VDD-VEE)>V5L
64CH Common Driver For Dot Matrix LCD
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CHAPTER 2
Driver IC Function Description
KS0107 Driver IC 64COM graphic driver for dot matrix LCD
Introduction
The KS0107B is an :CD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the KS0108B (64 channel segment drover.). The KS0107B is fabricated by low power CMOS high voltage process technology, and is composed of the liquid crystal display system in combination with the KS0108B (64 channel segment drover.).
(c) 1998 Intech LCD Group Ltd.
64CH Common Driver For Dot Matrix LCD
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AC Characteristics (VDD=4.5~5.5V, Ta=-30? ~+85? )
1. Master mode (MS=VDD, PCLK2=VDD, Cf=20pF, Rf=47KO)
CL2
0.7VDD 0.3VDD
t WLC tWHC tSU tDH tSU tD tDF tWHC
DIO1(SHL=VDD) DIO2(SHL=VSS) DIO2(SHL=VDD) DIO1(SHL=VSS) tD
FRM tDM M tR CLK1 tF CLK2 tF tR tWL1 t D12 t D21 tWH2 tWH1 tDM
0.7VDD 0.3VDD
Characteristic Data Setup Time Data Hold Time Data Delay Time FRM Delay Time M Delay Time CL2 Low Level Width CL2 High Level Width CLK1 Low Level Width CLK2 Low Level Width CLK1 High Level Width CLK2 High Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1,CLK2 Rise/Fall Time
Symbol tSU tDH tD tDF tDM tWLC tWHC tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR/t F
Min 20 40 5 -2 -2 35 35 700 700 2100 2100 700 700 -
Typ -
Max 2 2 150
Unit
?s
ns
(c) 1998 Intech LCD Group Ltd.
64CH Common Driver For Dot Matrix LCD
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Slave mode (MS=VSS)
CL2 (PLK2=VSS)
tF
tR
tWLC1 0.7VDD tWHC1 tSU tWLC2 tWLC 0.3VDD
CL2 (PLK2=VDD) tR DIO1(SHL=VDD) DIO2(SHL=VSS) Input Data DIO1(SHL=VDD) DIO2(SHL=VSS) Output Data
tF tD 0.7VDD 0.3VDD tH 0.7VDD 0.3VDD tHCL
Characteristics CL2 Low Level Width CL2 High Level Width CL2 Low Level Width CL2 High Level Width Data Setup Time Data Hold Time Data Delay Time Output Data Hold Time CL2 Rise/Fall Time
Symbol tWLC1 tWHC1 tWLC2 tWHL tSU tDH tD tH tR/tF
Min 450 150 150 450 100 100 10 -
Typ -
Max 200 30
Unit
ns
Note PCLK2=VSS PCLK2=VSS PCLK2=VDD PCLK2=VDD
*1
*1: Connect load CL=30pF OUTPUT 30pF
(c) 1998 Intech LCD Group Ltd.
64CH Common Driver For Dot Matrix LCD
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FUNCTIONAL DESCRIPTION
1.RC Oscillator The RC Oscillator generates CL2, M, FRM, of the KS0107B and CLK1, CLK2 of the KS0107B by the oscillation resister R and capacitor C. When selecting the master/slave, oscillation circuit is as following: 1) Master Mode
KS0107B R CR Rf Cf C R open
KS0107B CR C
open External clock
2)
Slave Mode
KS0107B R open CR VDD C open
2.Timing Generation circuit It generates CL2, M, FRM, CLK1, and CLK2 by the frequency from oscillation circuit. 1) Selection of Master/Slave (M/S) When M/S is "H", it generates CL2, M, FRM, CLK1, and CLK2 internally. When M/S is "L", it operates by receiving M, CLK2 from master device. Frequency Selection (FS) To adjust FRM by 70Hz, the oscillation frequency should be as following: FS H L Oscillation Frequency fOSC =430KHz fOSC =215KHz
2)
In the slave mode, it is connected to VDD.
(c) 1998 Intech LCD Group Ltd.
64CH Common Driver For Dot Matrix LCD
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3)
Duty Selection (DS1, DS2) It provides various duty selection according to DS1, DS2. DS1 L H DS2 L H L H DUTY 1/48 1/64 1/96 1/128
3.
Data shift & Phase Select Control 1) Phase Selection It is a circuit to shift data on synchronization or rising edge or falling edge of the CL2 according to PCLK2. PCLK2 H L 2) Phase Selection Data shift on rising edge of CL2 Data shift on falling edge of CL2
Data shift Direction Selection When M/S is connected to VDD, DIO1 and DIO2 terminal is only output. When M/S is connected to VSS, it depends on the SHL. MS H L SHL H L H L DIO1 Output Output Input Output DIO2 Output Output Output Input Direction of Data C1~C64 C64~C1 DIO1~C1~C64~DIO2 DIO2~C64~C1~DIO1
(c) 1998 Intech LCD Group Ltd.
64CH Segment Driver For Dot Matrix LCD
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CHAPTER 3
Driver IC Function Description
KS0108 Driver IC 64 SEG graphic driver for dot matrix LCD
Introduction
The KS0108B is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device consists of the display RAM, 64 bit data latch 64 bit drivers and decoder logics. It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix liquid crystal driving signals corresponding to stored data. The KS0108B composed of the liquid crystal display system in combination with the KS0107B(64 common driver).
AC Characteristics (VDD=4.5~5.5V ,VSS=0V, Ta=-30? ~+85? )
( 1) Clock Timing Symbol tCY tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR tF Min 2.5 625 625 1875 1875 625 625 Typ Max 20 150 150 Unit ?s
Characteristic CLK1, CLK2 Cycle Time CLK1`LOW'Level Width CLK2`LOW'Level Width CLK1`HIGH'Level Width CLK2`HIGH'Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1, CLK2 Rise Time CLK1, CLK2 Fall Time
ns
(c) 1998 Intech LCD Group Ltd.
64CH Segment Driver For Dot Matrix LCD
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tC Y C LK1 tF 0 .7 V D D 0 .3 V D D tW L 1 C LK2 tR
tW H 1
tD 1 2 0 .7 V D D 0 .3 V D D tF tW L 2
t D 21 t W H2
tF tC Y
( 2) .Display Control Timing Characteristic FRM Delay Time M Delay Time CL `LOW'Level Width CL`HIGH'Level Width Symbol tDF tDM tWL tWH Min -2 -2 35 35 Typ Max 2 2 Unit us
tWL CL 0.7VDD 0.3VDD tDF FRM 0.7VDD 0.3VDD tDM M 0. 7VDD 0.3VDD tDF
tWH
(c) 1998 Intech LCD Group Ltd.
64CH Segment Driver For Dot Matrix LCD
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( 3) . MPU Interface Characteristic E Cycle E High Level Width E Low Level Width E Rise Time E Fall Time Address Set-Up Time Address Hold Time Data Set-Up Time Data Delay Time Data Hold Time (Write) Data Hold Time (Read) Symbol tC tWH tWL tR tF tASU tAH tSU tD tDHW tDHR Min 1000 450 450 140 10 200 10 20 Typ Max 25 25 320 Unit
ns
tC E tWL tWH tR R/W tASU tASU CS1B,CS2B CS3,RS tDSU DB0~DB7 tDHW tAH tF
tAH
MPU Write timing
(c) 1998 Intech LCD Group Ltd.
64CH Segment Driver For Dot Matrix LCD
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tC E tWL tWH tR R/W tASU tASU CS1B,CS2B CS3,RS tD DB0~DB7 tWH tAH tAH tF
MPU Read timing
OPERATING PRINCIPLES & METHODS
1. I/O Buffer Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate regardless CS!B-CS3. Input register Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is written into input register. Then writing it into display RAM. Data latched for falling of the E signal and write automatically into the display data RAM by internal operation. Output register Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active mode and R/W and RS=H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active mode and R/W=H , RS=L, status data (busy check) can read out. To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data which is latched. That is to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read.
2.
3.
(c) 1998 Intech LCD Group Ltd.
64CH Segment Driver For Dot Matrix LCD
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RS L H
R/W L H L H
Function Instruction Status read (busy check) Data write (from input register to display data RAM ) Data read (from display data RAM to output register)
4.
Reset The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occurred. 1. Display off 2. Display start line register become set by 0.(Z-address 0) While RSTB is low, No instruction except status read can by accepted. Therefore, execute other instructions after making sure that DB4= (clear RSTB) and DB7=0 (ready) by status read instruction. The conditions of power supply at initial power up are shown in table 1. Table 1. Power Supply Initial Conditions Item Reset Time Rise Time Symbol tRS tR
4.5[V] t RS RSTB tR 0.7V DD 0.3V DD
Min 1.0 -
Typ -
Max 200
Unit us ns
V DD
5.
Busy flag Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in internal operating . When busy flag is low, KS0108B can accept the data or instruction. DB7indicates busy flag of the KS0108B.
E
Busy Flag
T Busy
1/fCLKfCLK is CLK1, CLK2 Frequency
(c) 1998 Intech LCD Group Ltd.
64CH Segment Driver For Dot Matrix LCD
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6.
Display On/Off Flip-Flop The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on segment output terminals regardless of display RAM data. The display on/off flip-flop can changes status by instruction. The display data at all segment disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read instruction. The display on/off flip-flop synchronized by CL signal. X Page Register X page register designates pages of the internal display data RAM. Count function is not available. An address is set by instruction. Y address counter Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased by 1 automatically by read or write operations of display data. Display Data RAM Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of liquid crystal display , write datra1. The other way , off state, writes 0. Display data RAM address and segment output can be controlled by ADC signal. ADC=H => Y-address 0: S1~Y address 63: S64 ADC=L => Y-address 0: S64~Yaddress 63: S1 ADC terminal connect the VDD or VSS.
7.
8.
9.
10. Display Start Line Register
The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data (DB<0.5>) of the display start line set instruction is latched in display start line register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of the liquid crystal display screen.
(c) 1998 Intech LCD Group Ltd.
64CH Segment Driver For Dot Matrix LCD
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Display Control Instruction
The display control instructions control the internal state of the KS0108B. Instruction is received from MPU to KS0108B for the display control. The following table shows various instructions.
Instruction Read Display Date
RS 1
RW 1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read data
Write Display Date
1
0
Write data
Status Read
0
1
Busy
0
ON/ OFF
Reset
0
0
0
0
Set Address (Y address) Set Display Start Line Set Address (X address)
0 0 0
0 0 0
0 1 1
1 1 0 1
Y address (0~63) Display start line (0~63) 1 1 Page (0~7)
Display On/off
0
0
0
0
1
1
1
1
1
0/1
Function Reads data (DB[7:0]) from display data RAM to the data bus. Writes data (DB[7:0]) into the DDRAM. After writing instruction, Y address is incriminated by 1 automatically Reads the internal status BUSY 0: Ready 1: In operation ON/OFF 0: Display ON 1: Display OFF RESET 0: Normal 1: Reset Sets the Y address at the column address counter Indicates the Display Data RAM displayed at the top of the screen. Sets the X address at the X address register. Controls the display ON or OFF. The internal status and the DDRAM data is not affected. 0: OFF, 1: ON
1.
Display On/Off The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D=0, it remains in the display data RAM. Therefore, you can make it appear by changing D=0 into D=1. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 1 1 D
2.
Set Address (Y Address) Y address (AC0~AC5) of the display data RAM is set in the Y address counter. An address is set by instruction and increased by 1 automatically by read or write operations of display data. RS 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
(c) 1998 Intech LCD Group Ltd.
64CH Segment Driver For Dot Matrix LCD
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3.
Set Page (X Address) X address (AC0~AC2) of the display data RAM is set in the X address register. Writing or reading to or from MPU is executed in this specified page until the next page is set. RS 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 1 DB2 AC2 DB1 AC1 DB0 AC0
4.
Display Start Line (Z Address) Z address (AC0~AC5) of the display data RAM is set in the display start line register and displayed at the top of the screen. When the display duty cycle is 1/64 or others (1/32~1/64), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed. RS 0 R/W 0 DB7 1 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
5.
Status Read RS 1 R/W 0 DB7 BUS Y DB6 0 DB5 ON/OFF DB4 RESET DB3 0 DB2 0 DB1 0 DB0 0
?? BUSY When BUSY is 1, the Chip is executing internal operation and no instructions are accepted. When BUSY is 0, the Chip is ready to accept any instructions. ?? ON/OFF When ON/OFF is 1, the display is on. When ON/OFF is 0, the display is off. ?? RESET When RESET is 1, the system is being initialized. In this condition, no instructions except status read can be accepted. When RESET is 0, initializing has finished and the system is in the usual operation condition. 6. Write Display Data Writes data (D0~D7) into the display data RAM. After writing instruction, Y address is increased by 1 automatically. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 1 D7 D6 D5 D4 D3 D2 D1 7. Read Display Data Reads data (D0~D7) from the display data RAM. After reading instruction, Y address is increased by 1 automatically. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 1 1 D7 D6 D5 D4 D3 D2 D1
DB0 D0
DB0 D0
(c) 1998 Intech LCD Group Ltd.

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